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Oldland CPU

Synthesizeable, 32-bit RISC CPU, SoC with toolchain

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JTAG crosses multiple clock domains, need to synchronize signals across those domains, simplest way is to use a dual port ram as a buffer for the command + data and then have ready + ack handshaking.

Memory map (Nx32-bit ram, word addresses):

JTAG commands:

Reads are 33 bits - a valid bit (32) + data (31:0). Commands are executed when address 0 is written.

Command list:

Register/memory operations may only be issued whilst the CPU is stopped.

For handshaking: