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Oldland CPU

Synthesizeable, 32-bit RISC CPU, SoC with toolchain

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Oldland Instruction Set

Arithmetic/Bitwise instructions

Call/Branch/Exception instructions

Load/Store instructions

Miscellaneous instructions

add

Class: 0, Opcode: 0

Description

Rd := Ra + OP2, OP2 may either be a register or a 13-bit signed immediate.

Instruction Operands

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addc

Class: 0, Opcode: 1

Description

Rd := Ra + OP2 + C, OP2 may either be a register or a 13-bit signed immediate.

Instruction Operands

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sub

Class: 0, Opcode: 2

Description

Rd := Ra - OP2, OP2 may either be a register or a 13-bit signed immediate.

Instruction Operands

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subc

Class: 0, Opcode: 3

Description

Rd := Ra - OP2 + C, OP2 may either be a register or a 13-bit signed immediate.

Instruction Operands

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lsl

Class: 0, Opcode: 4

Description

Rd := Ra << OP2, OP2 may either be a register or a 13-bit signed immediate.

Instruction Operands

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lsr

Class: 0, Opcode: 5

Description

Rd := Ra >> OP2, OP2 may either be a register or a 13-bit signed immediate.

Instruction Operands

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and

Class: 0, Opcode: 6

Description

Rd := Ra & OP2, OP2 may either be a register or a 13-bit signed immediate.

Instruction Operands

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xor

Class: 0, Opcode: 7

Description

Rd := Ra ^ OP2, OP2 may either be a register or a 13-bit signed immediate.

Instruction Operands

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bic

Class: 0, Opcode: 8

Description

Rd := Ra &= ~(1 << OP2), OP2 may either be a register or a 13-bit signed immediate.

Instruction Operands

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bst

Class: 0, Opcode: 9

Description

Rd := Ra |= (1 << OP2), OP2 may either be a register or a 13-bit signed immediate.

Instruction Operands

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or

Class: 0, Opcode: 10

Description

Rd := Ra | OP2, OP2 may either be a register or a 13-bit signed immediate.

Instruction Operands

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mul

Class: 0, Opcode: 11

Description

Rd := Ra * OP2, OP2 may either be a register or a 13-bit signed immediate.

Instruction Operands

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cmp

Class: 0, Opcode: 12

Description

Ra - OP2, OP2 may either be a register or a 13-bit signed immediate. The result is discarded.

Instruction Operands

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asr

Class: 0, Opcode: 14

Description

Rd := Ra ASR OP2, OP2 may either be a register or a 13-bit signed immediate.

Instruction Operands

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mov

Class: 0, Opcode: 15

Description

Rd := OP1, OP1 may be either a register or a 13-bit signed immediate.

Instruction Operands

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call

Class: 1, Opcode: 0

Description

PC := PC + (I << 2) if immediate, PC := Rb if register. LR := PC + 4.

Instruction Operands

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ret

Class: 1, Opcode: 1

Description

PC := LR

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b

Class: 1, Opcode: 4

Description

PC := PC + (i << 2) if immediate, PC := RB if register.

Instruction Operands

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bne

Class: 1, Opcode: 5

Description

If !Z PC := PC + (i << 2) if immediate, PC := RB if register.

Instruction Operands

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beq

Class: 1, Opcode: 6

Description

If Z PC := PC + (i << 2) if immediate, PC := RB if register.

Instruction Operands

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bgt

Class: 1, Opcode: 7

Description

If !C && !Z PC := PC + (i << 2) if immediate, PC := RB if register.

Instruction Operands

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blt

Class: 1, Opcode: 8

Description

If C && !Z PC := PC + (i << 2) if immediate, PC := RB if register.

Instruction Operands

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bgts

Class: 1, Opcode: 9

Description

If !Z && (N == O) PC := PC + (i << 2) if immediate, PC := RB if register.

Instruction Operands

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blts

Class: 1, Opcode: 10

Description

If N != O PC := PC + (i << 2) if immediate, PC := RB if register.

Instruction Operands

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bgte

Class: 1, Opcode: 12

Description

If !C PC := PC + (i << 2) if immediate, PC := RB if register.

Instruction Operands

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bgtes

Class: 1, Opcode: 13

Description

If N == O PC := PC + (i << 2) if immediate, PC := RB if register.

Instruction Operands

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blte

Class: 1, Opcode: 14

Description

If C || Z PC := PC + (i << 2) if immediate, PC := RB if register.

Instruction Operands

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bltes

Class: 1, Opcode: 11

Description

If (N != O) || Z PC := PC + (i << 2) if immediate, PC := RB if register.

Instruction Operands

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ldr32

Class: 2, Opcode: 0

Description

Rd := M[PC + I] (32-bits) if immediate, M[Ra + I] if register.

Instruction Operands

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ldr16

Class: 2, Opcode: 1

Description

Rd := M[PC + I] (16-bits) if immediate, M[Ra + I] if register.

Instruction Operands

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ldr8

Class: 2, Opcode: 2

Description

Rd := M[PC + I] (8-bits) if immediate, M[Ra + I] if register.

Instruction Operands

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str32

Class: 2, Opcode: 4

Description

M[PC + I] := Rb (32-bits) if immediate, M[Ra + I] := Rb if register.

Instruction Operands

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str16

Class: 2, Opcode: 5

Description

M[PC + I] := Rb (16-bits) if immediate, M[Ra + I] := Rb if register.

Instruction Operands

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str8

Class: 2, Opcode: 6

Description

M[PC + I] := Rb (8-bits) if immediate, M[Ra + I] := Rb if register.

Instruction Operands

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bkp

Class: 3, Opcode: 0

Description

Hardware breakpoint.

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nop

Class: 3, Opcode: 15

Description

No operation.

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movhi

Class: 3, Opcode: 11

Description

Rd := imm16 << 16.

Instruction Operands

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orlo

Class: 3, Opcode: 13

Description

Rd := Rb | imm16.

Instruction Operands

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cpuid

Class: 3, Opcode: 7

Description

Rd := cpuid[imm16].

Instruction Operands

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gcr

Class: 2, Opcode: 9

Description

Rd := control register N.

Instruction Operands

Privileged instruction.

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scr

Class: 2, Opcode: 10

Description

Control register N := ra.

Instruction Operands

Privileged instruction.

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swi

Class: 1, Opcode: 15

Description

Raise SWI imm13.

Instruction Operands

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rfe

Class: 1, Opcode: 2

Description

Return from exception.

Privileged instruction.

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cache

Class: 2, Opcode: 15

Description

Cache operation imm13, with index Ra if index valid.

Instruction Operands

Privileged instruction.

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gpsr

Class: 3, Opcode: 1

Description

Move the PSR into Rd.

Instruction Operands

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spsr

Class: 3, Opcode: 2

Description

Move the contents of Ra into the PSR.

Instruction Operands

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