View on GitHub

Oldland CPU

Synthesizeable, 32-bit RISC CPU, SoC with toolchain

Download this project as a .zip file Download this project as a tar.gz file


Oldland is a 32-bit RISC CPU targeted at FPGAs. The main features are: Oldland-core

Keynsham is a SoC using Oldland as the core and has a number of peripherals: Keynsham-soc

There is a C model along with Icarus and Verilator RTL simulations. The Keynsham SoC can be synthesized to run on a Terasic DE0 Nano or DE0-CV. There are ports of binutils, gcc, newlib, u-boot and RTEMS available.

The Terasic DE0-CV using an Altera Cyclone V and the DE0-nano board using an Altera Cyclone IV are the supported boards running at ~75MHz on slow silicon @85°C.



docker pull jamieiles/oldland-buildenv
git clone
git submodule init
git submodule update
docker run -it -v $(pwd):/data/oldland jamieiles/oldland-buildenv /bin/bash
mkdir BUILD
cmake /data/oldland/oldland-cpu
make all install -j16

Running On Hardware

Build the FPGA image in Quartus and load it onto the device. Run oldland-jtagd on the development machine, oldland-debug can then connect to the CPU over the virtual JTAG.


This project is currently licensed under GPLv2 except for oldland-jtagd which is under the Apache License v2.0.

About the Author

I’m Jamie Iles, you can reach me at I’m a software engineer, working at Oracle, leading the Ksplice engineering team.